1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly, to semiconductor memory devices having a test mode set in response to external control signals.
2. Description of the Background Art
With the recent increase in capacity of a semiconductor memory device, a function test of a memory cell array of a manufactured semiconductor memory device has been acquiring more importance. However, a time period required for such a function test has disadvantageously increased with an increase in the number of memory cells included in a memory cell array. Therefore, in order to reduce a time period required for such a function test of a semiconductor memory device, a so called on-chip test circuit system is recently adopted, on which system has been circuitry (referred to as a test circuit hereinafter) for such a function test is provided on the same chip as circuits constituting the semiconductor memory device are provided. Such an on-chip test circuit system is often employed for many DRAMs (Dynamic Random Access Memory), for example.
FIG. 13 is a block diagram showing an entire arrangement of a DRAM under the on-chip test circuit system. With reference to FIG. 13, a memory cell array 1 comprises memory cells (not shown) arranged in a matrix of rows and columns, word lines (not shown) each provided for each row, and bit line pairs (not shown) each pair provided for each column. Each memory cell is connected to a word line in the corresponding row and a bit line pair in the corresponding column. A row decoder 2 selects a word line and a column decoder 3 selects a bit line pair in response to row address signals RA0-RA9 and column address signals CA0-CA9 output from an address buffer 4, respectively.
Address buffer 4 receives either internal address signals Q0-Q9 output from a refresh counter 8 or external address signals A0-A10 in response to an internal row address strobe signal intRAS output from a RAS input circuit 10 and an internal column address strobe signal intCAS output from a CAS input circuit 12. Address buffer 4 outputs row address signals RA0-RA10 and column address signals CA0-CA10 in response to the received address signal. Address buffer 4 receives external address signals A0-A10 at the time of ordinary data reading and writing. Address buffer 4 receives internal address signals Q0-Q9 from refresh counter 8 at the time of refreshing, that is, rewriting data in a memory cell before storage data of the memory cell in memory cell array 1 is lost.
In response to an internal row address strobe signal intRAS from RAS input circuit 10, a refresh controller 9 controls refresh counter 8 to output an internal address signal in a fixed timing. In response to an output from refresh controller 9, refresh counter 8 generates internal address signals Q0-Q9 indicative of an address of a memory cell which storage data is to be refreshed.
Row decoder 2 selects a word line in response to row address signals RA0-RA9 from address buffer 4 in a timing of the internal row address strobe signal intRAS from RAS input circuit 10. Column decoder 3 selects a bit line pair in response to column address signals CA0-CA9 from address buffer 4 in a timing of the internal address strobe signal intCAS from CAS input circuit 12. More specifically, column decoder 3 controls an I/O gate 5 so as to electrically connect with an input buffer 6 or an output buffer 7, only a bit line pair corresponding to column address signals CA0-CA9 out of the bit line pairs in memory cell array 1.
I/O gate 5 includes transfer gates (not shown) each provided corresponding to each bit line pair in order to connect the corresponding bit line pair in memory cell array 1 with input buffer 6 and output buffer 7. Column decoder 3 selects a bit line pair by turning on, out of the transfer gates included in the I/O gate, only a transfer gate corresponding to a bit line pair at the column address designated by column address signal CA0-CA9.
A sense amplifier 15 amplifies data (read data) read out onto each bit line pair of memory cell array 1 in data reading. The bit line selecting operation of column decoder 3 allows the only bit line pair corresponding to the address signals, out of the bit line pairs in memory cell array 1, to be connected to output buffer 7 through I/O gate 5. Therefore, only the data read out onto the corresponding bit line pair out of the bit line pairs in memory cell array 1 is amplified by sense amplifier 15 and then, applied to a data output terminal Dout through output buffer 7.
In data writing, the data externally applied to a data input terminal Din is applied to I/O gate 5 through input buffer 6. Then, the externally applied data is written in a memory cell through a bit line pair selected by column decoder 3 out of the bit line pairs in memory array 1.
Data is transferred between I/O gate 5 and input buffer 6 or output buffer 7 on a maximum of 8-bit basis. In ordinary data writing and reading, however, an I/O controller 11 controls input buffer 6 and output buffer 7 to enable data transfer between I/O gate 5 and input buffer 6 or output buffer 7 on a four-bit basis. I/O controller 11 controls input buffer 6 and output buffer 7 in response to the most significant bit signals RA10 and CA10 of the row address signals RA0-RA10 and the column address signals CA0-CA10, respectively, output from address buffer 4, and to an internal write enable signal intWE output from a WE input circuit 13. More specifically, I/O controller 11 controls operation of output buffer 7 in response to row address signal RA10 and column address signal CA10 so as to output only the one bit data corresponding to the address designated by row address signal RA10 and column address signal CA10 out of the 4-bit data received by output buffer 7 from I/O gate 5, in the data reading where internal write enable signal intWE is at a "H" (logical high) level. Similarly, in data writing where internal write enable signal intWE is at a "L" (logical low) level, I/O controller 11 controls operation of input buffer 6 in response to row address signal RA10 and column address signal CA10 so as to receive data applied from data input terminal Din and apply the same to a transfer gate, out of the transfer gates in I/O gate 5, corresponding to a bit line pair at the address designated by row address signal RA10 and column address signal CA10. At the time of refreshing, the data read by output buffer 7 is again applied to I/O gate 5 as write data. In the refreshing, address buffer 4 receives internal address signals Q0-Q9 from refresh counter 8, for the storage of data of a memory cell at the address designated by internal address signals Q0-Q9.
In a test mode for a function test of the memory cells in memory cell array 1, data is transferred between I/O gate 5 and input buffer 6 or output buffer 7 on a 8-bit basis. In other words, column decoder 3, input buffer 6 and output buffer 7 operate in response to a test enable signal TE of "L" level from a test mode controller 14 in the test mode. More specifically, column decoder 3 selects a bit line pair by decoding only less significant bits column address signals CA0-CA9 while ignoring the most significant bit column address signal CA10 when receiving "L" level test enable signal TE from test mode controller 14. As a result, the number of bit line pairs selected each time by column decoder 3 is double the number in ordinary data reading and writing in number. Input buffer 6 is controlled by I/O controller 11 to apply 8-bit data applied to data input terminal Din in parallel to I/O gate 5 while receiving the "L" test enable signal TE from test mode controller 14. Similarly, output buffer 7 is controlled by I/O controller 11 to apply, to data output terminal Dout, the 8-bit data supplied in parallel from I/O gate 5 while receiving the "L" level test enable signal TE from test mode controller 14. Therefore, in a test mode, the data read out onto eight pairs of bit lines selected by column decoder 3 is externally output through output buffer 7, while externally applied 8-bit write data is applied in parallel to said eight pairs of bit lines through input buffer 6. A function test of a memory cell array is executed by verifying an agreement of predetermined write data to all or some of memory cells included in the memory cell array with read data therefrom. Therefore, the above-described operations of column decoder 3, input buffer 6 and output buffer 7 in a test mode automatically enables simultaneous tests for eight memory cells. In other words, memory cells in memory cell array 1 are automatically tested eight at a time in a test mode. A pattern of data to be written in a memory cell array for a test or the like varies depending on the type of the test.
Test mode controller 14 is a circuit for setting the DRAM to operate in a test mode or returning the operation mode of the DRAM from the test mode to a normal mode in response to the internal row address strobe signal intRAS from RAS input circuit 10, the internal column address strobe signal intCAS from CAS input circuit 12 and the internal write enable signal intWE from WE input circuit 13.
Specific operation of test mode controller 14 will be described with reference to FIGS. 14 and 15. FIG. 14 is a waveform diagram showing internal row address strobe signal intRAS, internal column address strobe signal intCAS and internal write enable signal intWE in a case where test mode controller 14 sets the DRAM to operate in a test mode. FIG. 15 is a waveform diagram showing the same signals in a case where test mode controller 14 returns the operation mode of the DRAM from the test mode to a normal mode.
With reference to FIG. 14, test mode controller 14 is activated when both internal signal intCAS (FIG. 14(b)) and intWE (FIG. 14(c)) are at a "L" level at time t1 when internal signal intRAS (FIG. 14(a)) falls. The activated test mode controller 14 drops the test enable signal TE (FIG. 14(d)) to a "L" level. Consequently, column decoder 3, input buffer 6 and output buffer 7 of FIG. 13 operate for the above-described test.
Conversely, with reference to FIG. 15, test mode controller 14 is inactivated in response to the internal signal intCAS (FIG. 15(b)) attaining a "L" level and the internal signal intWE (FIG. 15(c)) attaining a "H" level at time t2 when the internal signal intRAS (FIG. 15(a)) falls. The inactivated test mode controller 14 brings the test enable signal TE (FIG. 15(d)) to a "H" level. As a result, column decoder 3, input buffer 6 and output buffer 7 of FIG. 13 do not receive the "L" level test enable signal TE, thereby operating as described above for ordinary data reading and writing.
RAS input circuit 10, CAS input circuit 12 and WE input circuit 13 buffer an external row address strobe signal RAS, an external column address strobe signal CAS and an external write enable signal WE as external control signals, respectively, and outputs the same as the internal row address strobe signal intRAS, the internal column address strobe signal intCAS and the internal write enable signal intWE. The internal signals intRAS, intCAS and intWE take approximately the same waveforms as those of the external control signals RAS, CAS and WE. Since test mode controller 14 operates as described in the foregoing, in order to set the DRAM to operate in a test mode, the external control signal RAS should be dropped to a "L" level while both of the external control signal CAS and WE are at a "L" level. Conversely, in order to release the DRAM from the test mode, the external control signal RAS should be dropped to a "L" level while the external control signal CAS is at a "L" level and the external control signal WE is at a "H" level.
The timing of the control signal for dropping row address strobe signal RAS after a fall of column address strobe signal CAS as shown in FIGS. 14 and 15 is also employed in refreshing.
Again with reference to FIG. 13, a power-on reset circuit 18 is supplied with a voltage Vcc from an external power source (not shown) Power-on reset circuit 18 applies a "H" level one-shot pulse to predetermined circuits in the DRAM in response to a rise of the power supply voltage Vcc, that is, to a power supply to the DRAM. This one-shot pulse is referred to as a power-on reset signal POR. The power-on reset signal POR forces a potential at a predetermined node in the predetermined circuits to a level to be attained in an initialized state. As a result, the predetermined circuit portion is reset before starting its operation. Power-on reset signal POR is also applied to RAS input circuit 10, for example.
Although output POR of power-on reset circuit 18 is applied only to RAS input circuit 10 in FIG. 13, the output POR can be applied to other circuits as required in practice.
FIG. 16 is a circuit diagram showing the internal arrangement of RAS input circuit 10. With reference to FIG. 16, RAS input circuit 10 is a buffer circuit including an inverter 20 receiving external row address signal RAS as an input and an inverter 21 receiving the output of inverter 20 as an input. Inverter 20 includes a P channel MOS transistor Q1 and an N channel MOS transistor Q2 each receiving external row address strobe signal RAS at its gate, and a P channel MOS transistor Q3 and an N channel MOS transistor Q4 each receiving power-on reset signal POR at its gate. Transistors Q1 and Q2 are connected in series between power supply Vcc and ground GND. Transistor Q3 is provided between transistor Q1 and power supply Vcc. Transistor Q4 is connected in parallel to transistor Q2. The output end of inverter 20 is a node n2 between transistors Q1 and Q2. Inverter 21 includes a P channel MOS transistor Q5 and an N channel MOS transistor Q6 each receiving a potential at node N2 at its gate. Transistors Q5 and Q6 are connected in series between power supply Vcc and ground GND. The output end of inverter 21 is a node N4 between transistors Q5 and Q6. The potential at the node N4 is applied as an internal row address strobe signal intRAS to a predetermined circuit portion.
A "H" level potential of output end N2 of inverter 20 turns on transistor Q6 of inverter 21, whereby the potential at node N4 attains a "L" level. Conversely, a "L" level potential at node N2 turns on transistor Q5 of inverter 21, whereby the potential at node N4 attains a "H" level.
When transfer gate Q3 is ON and transistor Q4 is OFF in inverter 20, the source of transistor Q1 is electrically connected to power supply Vcc and transistor Q4 exercises no effect on the potential at node N2. Therefore, in this case, the arrangement of inverter 20 is the same as that of inverter 21 in operation. In other words, the potential level of the external row address strobe signal RAS applied to input end N1 of inverter 20 is inverted by the switching operation of transistors Q1 and Q2, the inverted potential appears at output end N2 of inverter 20. Therefore, the internal row address strobe signal intRAS takes the same waveform as that of the external row address strobe signal RAS when output POR of power-on reset circuit 18 of FIG. 13 is at a "L" level, that is, when no power-on reset signal is applied to RAS input circuit 10. However, if transistor Q3 is OFF and transistor Q4 is ON in inverter 20, the potential at node N2 attains a "L" level in response to a low potential of ground GND applied through transistor Q4, irrespective of conduction states of transistors Q1 and Q2. In this case, therefore, the potential at output end N4 of RAS input circuit 10 attains a "H" level, irrespective of the potential level of the external row address strobe signal RAS. In other words, the internal row address strobe signal intRAS attains a "H" level when RAS input circuit 10 receives a power-on reset signal, irrespective of the potential level of the external row address strobe signal RAS. That is, while RAS input circuit 10 receives a power-on reset signal, inverter 20 is inactivated to inactivate a buffering operation of RAS input circuit 10.
RAS input circuit 10 is structured as describe to be activated/inactivated in response to output POR of power-on reset circuit 18. The internal row address strobe signal intRAS is therefore once forced to a predetermined level "H", after a power supply, in response to the output of the "H" power-on reset signal from power-on reset circuit 18 at the power supply. Thereafter, the potential of the internal row address strobe signal intRAS changes following the potential change of the external row address strobe signal RAS to enable a predetermined circuit portion to be controlled in response to the external address strobe signal RAS. This is for forcing such circuit portions to be controlled in response to an external row address strobe signal RAS as row decoder 2, address buffer 4 and refresh controller 9 to enter an initialized state. In other words, the internal row address strobe signal intRAS attaining a "H" level at a power supply forces a node receiving an internal row address strobe signal intRAS in each circuit portion to have a potential allowing the circuit portion to be initialized.
As described in the foregoing, in a conventional DRAM including a test circuit on the same chip, a circuit portion (test mode controller 14 of FIG. 13) designating a test mode operates in response to internal signals intRAS, intCAS and intWE obtained by buffering external signals RAS, CAS and WE. However, the circuit portion designating a test mode might malfunction at the power supply because of the arrangement of the circuit portion (RAS input circuit 10 of FIG. 13) buffering an external signal RAS (see FIG. 17). This phenomenon will be more specifically described in the following with reference to FIGS. 17 through 14. FIGS. 17 through 14 are waveform diagrams explaining why such a phenomenon is caused.
With reference to FIG. 13, the conventional RAS input circuit 10 is controlled by output POR of power-on reset circuit 18. Therefore, a rise of power supply voltage Vcc (FIG. 17(a)) upon a power supply is followed by output POR (FIG. 17(b)) of power-on reset circuit 18 attaining a "H" level for a fixed time period, with reference to FIG. 17. While output POR of power-on reset circuit 18 is at a "H" level, that is, while RAS input circuit 10 receives a power-on reset signal, output intRAS (FIG. 17(d)) of RAS input circuit 10 attains a "H" level, irrespective of the external row address strobe signal RAS (FIG. 17(c)).
All of the three external control signals RAS, CAS and WE controlling test mode controller 14 are brought to a "H" level after a predetermined circuit portion is initialized in response to a power-on reset signal after a power supply. More specifically, the low active external control signals RAS, CAS and WE are brought to a "L" level or to a "H" level in a predetermined timing after once brought to a "H" level, thereby to control the predetermined circuit portion. Therefore, as shown in FIGS. 17(c), 17(e) and 17(f), respectively, the external control signals RAS, CAS and WE are at a "L" level in all the periods including a period when output POR of power-on reset circuit 18 is at a "H" level. On the other hand, CAS input circuit 12 and WE input circuit 13, without receiving a power-on reset signal, buffers the external control signals CAS and WE and outputs the same after a power supply. As a result, the internal column address strobe signal intCAS and the internal write enable signal intWE take approximately the same waveforms as those of the external signals CAS and WE, irrespective of the potential level of output POR of power-on reset circuit 18. Both of the internal column address strobe signal intCAS and the internal write enable signal intWE are, therefore, at a "L" level at t3 when the internal row address strobe signal intRAS falls. As described above, test controller 14 outputs a "L" level test enable signal TE designating a test mode in response to the internal signal intRAS falling to a "L" when both of the internal signals intCAS and intWE are at a "L" level. In this way, the DRAM of FIG. 13 is set to operate in a test mode in response to a fall of the internal signal intRAS in response to a fall of the output POR of power-on reset circuit 18. In other words, a conventional DRAM is set to operate in a test mode before receiving external control signals RAS, CAS and WE for enabling circuit operations for data reading and writing. Once the DRAM enters a test mode, it does not return to a normal mode unless the internal signal RAS falls to bring output TE of test mode controller 14 to a "H" level when internal signal CAS is at a "L" and the internal signal WE is at a "H" level. Therefore, even when ordinary data reading and writing should be performed by dropping one of the external signals RAS, CAS and WE in a predetermined timing after a power supply, the DRAM set to operate in a test mode does not accurately accept applied external address signals and the data to be written, etc. but it malfunctions.
In order to avoid such a problem, conventionally, the external signal RAS should be dropped once in a period when trial external signals RAS, CAS and WE are applied to the DRAM prior to the application of the external signals RAS, CAS and WE for ordinary data reading and writing, that is, in a dummy cycle. In other words, by setting a time point at which the internal signal intRAS falls when the internal signals intCAS and intWE are at a "L" level and a "H" level, respectively, the DRAM at an initialized state is reliably set to operate in a normal mode.
The DRAM might automatically enter the test mode by accident after a power supply not only at a fall of the power-on reset signal as described above but also at a first rise of the external row address strobe signal RAS after the power supply.
It is assumed, for example, that a first rise time of the external row address strobe signal RAS is long after a power supply because of the large total load to be driven by the external row address strobe signal RAS or the like. With reference to FIG. 18, when external row address strobe signal RAS rises slowly as shown in FIG. 18(b) after a rise of a power supply voltage to Vcc (FIG. 18(a)) upon a power supply, output intRAS of RAS input circuit 10 of FIG. 13 rises with a delay time of T after external row address strobe signal RAS starts rising as shown in FIG. 18(b). External row address strobe signal RAS rises after one-shot pulse is output from power-on reset circuit 18, which is supposed to be followed by a potential rise of output signal intRAS from RAS input circuit 10. As shown in FIG. 16, however, RAS input circuit 10 includes inverter 20 inverting external row address strobe signal RAS. With reference to FIG. 16, the potential at node N2 therefore should attain a logical level opposite to that of the potential of external row address strobe signal RAS to allow the potential of internal row address strobe signal intRAS obtained at node N4 to have the same logical level as that of the potential of external row address strobe signal RAS applied to node N1. That is, the potential of external row address strobe signal RAS should exceed a threshold voltage V1 of the inverter 20. A threshold voltage of a CMOS inverter is ordinarily set to an intermediate value between a potential of a low potential source and a potential of a high potential source connected thereto. Threshold voltage V1 of inverter 20 has an approximately intermediate value (Vcc/2) between the potentials of power supply voltage Vcc ("H" level) and ground GND ("L" level).
With reference to FIG. 18 in addition to FIG. 16, the external signal RAS rising slowly results in an increase in a time period required for the potential at node N1 to exceed threshold voltage V1 of inverter 20 in FIG. 16. Therefore, internal row address strobe signal intRAS is late in rising than external row address strobe signal RAS, by a time period required for the potential of external row address strobe signal RAS to change from a ground potential to threshold voltage V1 of inverter 20.
As described above, the logical level of the potential of output signal intRAS from RAS input circuit 10 is low only when the potential of external signal RAS is equal to or less than threshold voltage V1 of inverter 20. As a result, the following problem arises when external signal RAS rises slowly and includes noise at around threshold voltage V1 of inverter 20 after a power supply as shown in FIG. 19(b).
The potential of external signal RAS may become higher than threshold voltage V1 of inverter 20 and then, become lower than the same before completely rising to a "H" level (see FIG. 19(b)). In such a case, the inverter 20 takes external signal RAS equal to or above said threshold voltage V1 for "H" level and the signal RAS lower than threshold voltage V1 for "L" level in RAS input circuit 10. As shown in FIG. 19(c), the potential of internal signal intRAS therefore attains a "H" level in the period T1 when the potential of external signal RAS exceeds said threshold voltage V1 and drops to a "L" level when the same becomes said threshold voltage V1 or lower thereafter. Then, internal signal intRAS again attains a "H" level when external signal RAS attains a level equal to or above said threshold voltage V1 thereafter in spite of fluctuation due to noise. As described in the foregoing, noise included in external signal RAS at around the threshold V1 causes internal signal intRAS to have false leading edge and trailing edge.
On the other hand, with an external signal rising slowly, when external row address strobe signal RAS rises prior to external column address strobe signal CAS and external write enable signal WE after a rise of power supply voltage Vcc (FIG. 19(a)) upon a power supply, it is possible that both of the internal column address strobe signal intCAS (FIG. 19(d)) and internal write enable signal intWE (FIG. 19(e)) attain a "L" level in a period when external row address strobe signal RAS is not completely brought to a "H" level. In such a case, both of the internal column address strobe signal intCAS and internal write enable signal intWE are at a "L" level at time t4 at which internal row address strobe signal intRAS falls due to the noise. Therefore, test mode controller 14 of FIG. 13 outputs a "L" level test enable signal TE in response to the fall of internal signal RAS due to the noise. As a result, the DRAM of FIG. 13 enters the test mode before external signals RAS, CAS and WE are once brought to a "H" level for operating the DRAM in practice.
A period is not shown in FIGS. 18 and 19 when internal signal RAS attains a "H" level in response to a power-on reset signal immediately after a power supply.
As such a buffer circuit for buffering external signals as input circuits 10, 12 and 13 of FIG. 13, a circuit may be used wherein an input potential corresponding to a switching point of an output potential from a "H" level to a "L" level is set slightly lower than the threshold voltage (Vcc/2) of a CMOS inverter and an input potential corresponding to a switching point of the output potential from a "L" to "H" is set to the threshold voltage (Vcc/2) of the CMOS inverter. Referring to FIG. 6, such circuit can be implemented by adding a small-sized P channel MOS transistor connected between the input end of inverter 21 and power supply Vcc and having a gate receiving the output potential of inverter 21.
In the following description, a buffer circuit will be also referred to as a hysteresis buffer, which has different input potentials; one of which corresponds to a switching point of an output potential from a "H" level to "L" level and the other corresponds to a switching point of the same from a "L" level to a "H" level. As described above, as the conventional input circuits 10, 12 and 13, a buffer circuit is commonly used in which a difference between these two input potentials (threshold voltage) is small, that is, a hysteresis buffer is used in which a difference between hysteresis of an output potential with an input potential being increased and hysteresis of an output potential with the input potential being reduced is small.
Resetting of row decoder 2, address buffer 4, refresh controller 9 and the like by the output of power-on reset circuit 18 can be implemented by inputting the output POR of power-on reset circuit 18 not to RAS input circuit 10 but to a circuit arranged in the succeeding stage to RAS input circuit, that is, to a circuit which is located in the preceding stage to circuits to be reset (row decoder 2, address buffer 4, refresh controller 9 and the like) and is located more closer to these. In such a case, RAS input circuit 10 does not exhibit such problem as described above caused by the output POR of power-on reset circuit 18. However, the above-described hysteresis buffer used as RAS input circuit 10 causes the following problems.
That is, the level of internal row address strobe signal intRAS changes from "H" to "L" only when the potential of external row address strobe signal RAS becomes lower than a conventional threshold voltage (Vcc/2). Hence, the operation margin of RAS input circuit 10 for input signal RAS is reduced.
Furthermore, a potential on an internal row address strobe signal intRAS later in changing than an external row address strobe signal RAS results in delay in a start of operations for data writing and data reading by such circuits as row decoder 2, address buffer 4 and refresh controller 9 which are to be controlled by the external row address strobe signal RAS. Therefore, the use of a hysteresis buffer as RAS input circuit 10 increases an access time of the semiconductor memory device.